Field of Invention
The present invention relates to a wafer coating system and a method of manufacturing a chip package using the wafer coating system.
Description of Related Art
Along with the trends of electronic devices toward lighter and more compact, the semiconductor chip corresponding to the electronic device has a reduced size and increased wiring density. Therefore, it is more difficult and challenging to fabricate a semiconductor chip package in the subsequent process for the semiconductor chip. Wafer-level chip package is a method of packaging the semiconductor chip, which the method means all the chips are packaged and tested after completion of manufacturing these chips on the wafer, and then the wafer is cut into single chip packages.
Since the size of the semiconductor chip is decreased and the functional density on the semiconductor chip is increased, the insulating property of the wafer is one of the important research directions in the chip packaging techniques to avoid erroneous electrical connection. Generally, an oxide is used to prepare an isolation layer of the chip, but the oxide is expensive, and the process of depositing the oxide is complicated and time-consuming, and thus decreases efficiency of the process. Therefore, the oxide is gradually replaced by an epoxy material to prepare the isolation layer of the chip package.
However, the epoxy material is easily affected by the gravity to aggregate, which is not benefit for forming uniform isolation layer, and thus decreases the yield of the chip package.